Abstract

In todays real time world network on chip (NoC) plays a major role in fast communication between entities. The need for NoC hardware is in demand based on requirement for fast communication with large data bandwidth. In this paper, an efficient field programmable gate array (FPGA) based NoC architecture for data communication is proposed. The router is designed with 4 ports using proposed controller unit, novel first-in first-out (FIFO) architecture and XY routing logic. The proposed controller unit comprises of MUX based architecture to support the data transfer in East, West, North and South directions using respective select lines with flip-flops connected to the output of multiplexers to achieve delay synchronization. A novel FIFO architecture is designed using a counter and decision unit which are used to keep track of incoming data using signal mem_empty or mem_full. The XY routing logic is used to communicate between the routers and a test sample data is chosen to validate the routing path between source and destination using XY routing logic. The proposed routing architecture is tested on SPARTAN-6-XC6SLX45 board. It is observed that the performance parameters such as slice registers, power dissipation and maximum operating frequency are 290, 38.35 mW and 220.729 MHz respectively.

Keyword

NoC, Controller unit, FIFO, XY routing algorithm.

Cite this article

Refference

[1][1]Bhanwala A, Kumar M, Kumar Y. FPGA based design of low power reconfigurable router for network on chip (NoC). In international conference on computing, communication & automation 2015 (pp. 1320-6). IEEE.

[2][2]Kumar M, Kumar K, Gupta SK, Kumar Y. FPGA based design of area efficient router architecture for network on chip (NoC). In international conference on computing, communication and automation 2016 (pp. 1600-5). IEEE.

[3][3]Shermi S, Arun CS. A novel architecture of bidirectional NoC router using flexible buffer. In international conference on emerging technological trends 2016 (pp. 1-6). IEEE.

[4][4]Sharma N, Gadag S. An efficient way to increase performance by using low power reconfigurable routers. IOSR Journal of Electronics and Communication Engineering. 2013; 8(6):39-44.

[5][5]Langar M, Bourguiba R, Mouine J. Virtual channel router architecture for network on chip with adaptive inter-port buffers sharing. In international multi-conference systems, signals & devices 2016 (pp. 691-4). IEEE.

[6][6]Mondal HK, Gade SH, Kishore R, Deb S. Power and performance-aware fine-grained reconfigurable router architecture for NoC. In sixth international green and sustainable computing conference (IGSC) 2015 (pp. 1-6). IEEE.

[7][7]Xia L, Ma Y, Xu N. Defect-tolerant routing algorithm for low power NoCs based on buffer-shared router architecture. In international conference on communications, circuits and systems 2013(pp. 391-4). IEEE.

[8][8]Yang W, Jung JH, Kim YC. Performance evaluation of energy saving in core router architecture with low power idle for OBS networks. International conference on information networking 2012 (pp. 318-23). IEEE.

[9][9]Roca A, Flich J, SIlla F, Duato J. A latency-efficient router architecture for CMP systems. In euromicro conference on digital system design: architectures, methods and tools 2010 (pp. 165-72). IEEE.

[10][10]Cheshmi K, Trajkovic J, Soltaniyeh M, Mohammadi S. Quota setting router architecture for quality of service in GALS NoC. In international symposium on rapid system prototyping 2013 (pp. 44-50). IEEE.

[11][11]Seitanidis I, Psarras A, Dimitrakopoulos G, Nicopoulos C. Elastistore: an elastic buffer architecture for network-on-chip routers. In proceedings of the conference on design, automation & test in Europe 2014 (pp.1-6). European Design and Automation Association.

[12][12]Ramani S, Sundararajan J. A case study on NoC router architecture for optimizing the latency. In international conference on advanced computing and communication systems 2013 (pp. 1-4). IEEE.

[13][13]Poluri P, Louri A. Shield: a reliable network-on-chip router architecture for chip multiprocessors. IEEE Transactions on Parallel and Distributed Systems. 2016; 27(10):3058-70.

[14][14]Yan P, Jiang S, Sridhar R. A novel fault-tolerant router architecture for network-on-chip reconfiguration. In international system-on-chip conference 2015 (pp. 292-7). IEEE.

[15][15]Jayan G, Pavitha PP. FPGA implementation of an efficient router architecture based on DMC. In international conference on emerging technological trends 2016 (pp. 1-6). IEEE.

[16][16]Shenbagavalli S, Karthikeyan S. An efficient low power NoC router architecture design. In online international conference on green engineering and technologies 2015 (pp. 1-8). IEEE.

[17][17]Haria S, Ganegedara T, Prasanna V. Power-efficient and scalable virtual router architecture on FPGA. In international conference on reconfigurable computing and FPGAs 2012 (pp. 1-7). IEEE.

[18][18]Fatima A, Waseem SM. Rapid on-chip communication in 2D networks using 8-port router in a multicast environment and their realization. International Journal of Science and Research. 2014; 3(9):117-20.

[19][19]Chawade SD, Gaikwad MA, Patrikar RM. Review of XY routing algorithm for network-on-chip architecture. International Journal of Internet Computing. 2012; 1(4):48-52.

[20][20]Sahu S, Kittur HM. Area and power efficient network on chip router architecture. In conference on information & communication technologies 2013 (pp. 855-9). IEEE.

[21][21]Suraj MS, Muralidharan D, Kumar KS. A HDL based reduced area NOC router architecture. In international conference on emerging trends in VLSI, embedded system, NANO electronics and telecommunication system 2013 (pp. 1-3). IEEE.

[22][22]Khodwe A, Bhoyar C N. Area efficient FPGA based bidirectional network on chip router through virtual channel regulator. International Journal of Computer Trends and Technology.2013; 4(7):2107-12.

[23][23]Yadav MP, Singh MA. Area efficient router architecture design of network-on-chip (NOC). International Research Journal of Engineering and Technology.2016; 3(6):555-8.

[24][24]Basha SS, Babu TR. Design of intelligent power saving (IPS) architecture for reducing power and area in NoC. In international conference on innovations in information, embedded and communication systems 2015(pp.1-8). IEEE.