International Journal of Advanced Technology and Engineering Exploration (IJATEE) ISSN (P): 2394-5443 ISSN (O): 2394-7454 Vol - 9, Issue - 93, August 2022
  1. 1
    Google Scholar
Analysis of subthreshold swing in junctionless cylindrical surrounding gate MOSFET using Gaussian doping profile

Hakkee Jung

Abstract

The subthreshold swing (SS) model is presented for a junctionless cylindrical surrounding gate (JLCSG) metal oxide semiconductor field effect transistor (MOSFET) with a Gaussian doping profile. Since the Poisson’s equation using the Gaussian doping profile has no closed form solution in cylindrical coordinate, the potential distribution is obtained using the Taylor series expansion of the error function and exponential function. The SS model presented in this study is considered to be reasonable, comparing the SSs of 3D simulation and other papers. As a result, the smaller the projected range Rp and straggle〖 σ〗_p , the smaller the SS. However, when the projected range is 1/2 of the silicon radius R, the SS remains constant regardless of the change of the straggle. The SS increases when straggle increases in RpR/2. Therefore, the SS should be kept low by adjusting the projected range and straggle in JLCSG MOSFET with gaussian doping profile.

Keyword

Cylindrical surrounding gate, Junctionless, Gaussian, Projected range, Straggle, Subthreshold swing.

Cite this article

Refference

[1][1]Strempel K, Römer F, Yu F, Meneghini M, Bakin A, Wehmann HH, et al. Vertical 3D gallium nitride field-effect transistors based on fin structures with inverted p-doped channel. Semiconductor Science and Technology. 2020; 36(1):1-9.

[2][2]Owyeung RE, Sonkusale S, Panzer MJ. Opportunities for ionic liquid/ionogel gating of emerging transistor architectures. Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 2021; 39(1).

[3][3]Moon J, Nam S, Joo CW, Sung C, Kim HO, Cho SH, Park CW. Issues on monolithic 3D integration techniques for realizing next generation intelligent devices. Electronics and Telecommunications Trends. 2021; 36(3):12-22.

[4][4]https://www.copperpodip.com/post/gate-all-around-gaa-get-going-beyond-the-3-nanometer-mask. Accessed 18 July 2022.

[5][5]Subramanian S, Hosseini M, Chiarella T, Sarkar S, Schuddinck P, Chan BT, et al. First monolithic integration of 3d complementary fet (cfet) on 300mm wafers. In symposium on VLSI technology 2020 (pp. 1-2). IEEE.

[6][6]Gu Y, Wang C, Kim N, Zhang J, Wang TM, Stowe J, et al. Three-dimensional transistor arrays for intra-and inter-cellular recording. Nature Nanotechnology. 2022; 17(3):292-300.

[7][7]Shin J, Shin C. Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET. Solid-State Electronics. 2019; 153:12-5.

[8][8]https://www.marketinsightsreports.com/reports/07158462998/global-finfet-cpu-matket-research-report-2022/inquiry?Mode=A28. Accessed 19 July 2022.

[9][9]Madhavi KB, Tripathi SL. Strategic review on different materials for FinFET structure performance optimization. In IOP conference series: materials science and engineering 2020 (pp.1-8). IOP Publishing.

[10][10]Park J, Kim J, Showdhury S, Shin C, Rhee H, Yeo MS, Cho EC, Yi J. Electrical characteristics of bulk FinFET according to spacer length. Electronics. 2020; 9(8):1283.

[11][11]https:// eepower.com/technical-articles/what-is-a-finfet. Accessed 19 July 2022.

[12][12]https://english.cas.cn/newsroom/research_news/ tech/202003/t20200310_230971.shtml. Accessed 19 July 2022.

[13][13]Zhang S. Review of modern field effect transistor technologies for scaling. In journal of physics: conference series 2020 (pp. 1-8). IOP Publishing.

[14][14]Yerragopu R, Priya DP, Kasthuribha JK. Modeling, optimization and comprehensive comparative analysis of 7nm FinFET and 7nm GAAFET devices. In AIP conference proceedings 2020 (pp.1-8). AIP Publishing LLC.

[15][15]Das UK, Bhattacharyya TK. Opportunities in device scaling for 3-nm node and beyond: FinFET versus GAA-FET versus UFET. IEEE Transactions on Electron Devices. 2020; 67(6):2633-8.

[16][16]Dash S, Mishra GP. An analytical model of the surface-potential-based source-pocket-doped cylindrical-gate tunnel FET with a work-function-modulated metal gate. Journal of Computational Electronics. 2020; 19(2):591-602.

[17][17]Shafizade D, Shalchian M, Jazaeri F. Charge-based modeling of ultra narrow junctionless cylindrical nanowire FETs. Solid-State Electronics. 2021.

[18][18]Abd EHH, Iñíguez B, Guitart JR. Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all-around-based MOSFETs. IEEE Transactions on Electron Devices. 2007; 54(3):572-9.

[19][19]Ahn MJ, Saraya T, Kobayashi M, Hiramoto T. Variability characteristics and corner effects of gate-all-around (GAA) p-type poly-Si junctionless nanowire/nanosheet transistors. Japanese Journal of Applied Physics. 2021; 60(SB).

[20][20]Nowbahari A, Roy A, Marchetti L. Junctionless transistors: State-of-the-art. Electronics. 2020; 9(7):1174.

[21][21]Ionescu AM. Nanowire transistors made easy. Nature Nanotechnology. 2010; 5(3):178-9.

[22][22]Bousari NB, Anvarifard MK, Haji-Nasiri S. Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering. AEU-International Journal of Electronics and Communications. 2019; 108:226-34.

[23][23]Lü WF, Dai L. Impact of work-function variation on analog figures-of-merits for high-k/metal-gate junctionless FinFET and gate-all-around nanowire MOSFET. Microelectronics Journal. 2019; 84:54-8.

[24][24]Kumar A, Tiwari PK, Roy JN. Subthreshold model of asymmetric GAA junctionless FETs with scaled equivalent oxide thickness. Microelectronics Journal. 2022.

[25][25]Nowbahari A, Roy A, Nadeem AM, Marchetti L. Analysis of an approximated model for the depletion region width of planar junctionless transistors. Electronics. 2019; 8(12):1-19.

[26][26]Wang Y, Tang Y, Sun LL, Cao F. High performance of junctionless MOSFET with asymmetric gate. Superlattices and Microstructures. 2016; 97:8-14.

[27][27]Kumar B, Chaujar R. Analog and RF performance evaluation of junctionless accumulation mode (JAM) gate stack gate all around (GS-GAA) FinFET. Silicon. 2021; 13(3):919-27.

[28][28]Priyadarshani KN, Singh S, Mohammed MK. Gate-all-around junctionless FET based label-free dielectric/charge modulation detection of SARS-CoV-2 virus. RSC Advances. 2022; 12(15):9202-9.

[29][29]Jeon DY. Channel geometry-dependent threshold voltage and transconductance degradation in gate-all-around nanosheet junctionless transistors. AIP Advances. 2021; 11(5).

[30][30]Liu TY, Pan FM, Sheu JT. Characteristics of gate-all-around junctionless polysilicon nanowire transistors with twin 20-nm gates. IEEE Journal of the Electron Devices Society. 2015; 3(5):405-9.

[31][31]Jaafar H, Aouaj A, Bouziane A, Iñiguez B. An analytical drain current model for cylindrical gate DMG-GC-DOT MOSFET. International Journal of Electronics Letters. 2019; 7(4):458-72.

[32][32]Karbalaei M, Dideban D, Heidari H. A sectorial scheme of gate-all-around field effect transistor with improved electrical characteristics. Ain Shams Engineering Journal. 2021; 12(1):755-60.

[33][33]Maduagwu UA, Srivastava VM. Analytical performance of the threshold voltage and subthreshold swing of CSDG MOSFET. Journal of Low Power Electronics and Applications. 2019; 9(1):1-20.

[34][34]Kim JH, Sun WK, Park SH, Lim HI, Shin HS. A compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate metal-oxide-semiconductor field-effect transistors. JSTS: Journal of Semiconductor Technology and Science. 2011; 11(4):278-86.

[35][35]Thoti N, Li Y. Design of GAA nanosheet ferroelectric area tunneling FET and Its significance with DC/RF characteristics including linearity analyses. Nanoscale Research Letters. 2022; 17(1):1-11.

[36][36]Jung H. Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-k oxide. AIMS Electronics and Electrical Engineering. 2022; 6(2):108-23.

[37][37]Li C, Zhuang Y, Han R, Jin G. Subthreshold behavior models for short-channel junctionless tri-material cylindrical surrounding-gate MOSFET. Microelectronics Reliability. 2014; 54(6-7):1274-81.

[38][38]Lagraf F, Rechem D, Guergouri K, Zaabat M. Channel length effect on subthreshold characteristics of junctionless trial material cylindrical surrounding-gate MOSFETs with High-k gate dielectrics. Journal of Nano-and Electronic Physics. 2019; 11(2).

[39][39]Nandi A, Saxena AK, Dasgupta S. Analytical modeling of a double gate MOSFET considering source/drain lateral Gaussian doping profile. IEEE Transactions on Electron Devices. 2013; 60(11):3705-9.

[40][40]Shukla AK, Nandi A, Dasgupta S. Modeling source/drain lateral Gaussian doping profile of DG-MOSFET using green’s function approach. Solid-State Electronics. 2020.

[41][41]Saha P, Banerjee P, Dash DK, Sarkar SK. Modeling short channel behavior of proposed work function engineered high-k gate stack DG MOSFET with vertical gaussian doping. In electron devices Kolkata conference 2018 (pp. 32-6). IEEE.

[42][42]Li C, Zhuang Y, Di S, Han R. Subthreshold behavior models for nanoscale short-channel junctionless cylindrical surrounding-gate MOSFETs. IEEE Transactions on Electron Devices. 2013; 60(11):3655-62.

[43][43]Singh B, Gola D, Singh K, Goel E, Kumar S, Jit S. Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. IEEE Transactions on Electron Devices. 2016; 63(6):2299-305.

[44][44]Sood H, Srivastava VM, Singh G. Performance analysis of undoped and Gaussian doped cylindrical surrounding-gate MOSFET with its small signal modeling. Microelectronics Journal. 2016; 57:66-75.

[45][45]Mehta H, Kaur H. Impact of Gaussian doping profile and negative capacitance effect on double-gate junctionless transistors (DGJLTs). IEEE Transactions on Electron Devices. 2018; 65(7):2699-706.

[46][46]http://www.businesskorea.co.kr/news/articleView.html?idxno=94884. Accessed 8 August 2022.

[47][47]https://www.phonearena.com/news/samsung-first-to-ship-3nm-gaa-chips_id141505. Accessed 8 August 2022.

[48][48]Banerjee P, Das J. Threshold voltage modeling of gaussian-doped dual work function material cylindrical gate-all-around (CGAA) MOSFET considering the effect of temperature and fixed interface trapped charges. Microelectronics Journal. 2022.

[49][49]Gupta SK. Threshold voltage model of junctionless cylindrical surrounding gate MOSFETs including fringing field effects. Superlattices and Microstructures. 2015; 88:188-97.