Abstract

Testing is a critical aspect of integrated circuit (IC) design, aimed at ensuring thorough evaluation of all nodes within the designs netlist to identify potential defects. The effectiveness of design for testability (DFT) relies on assessing the observability and controllability of each node within the architecture. These attributes form the foundation of DFT, enabling optimal test coverage (TC) with minimal test time (TT). The rigor of design testing is directly linked to the number of patterns used, with crucial parameters, such as multi-voltage conditions, temperature variations, and comprehensive testing methodologies playing key roles during the process. This methodology integrates techniques, such as scan insertion (SI), automatic test pattern generation (ATPG), embedded deterministic testing, and pattern simulation. The primary goal is to compress and minimize test data volume (TDV) and TT. ATPG plays a pivotal role in this approach by generating patterns tailored to meet compression requirements. Simulation validates the effectiveness of these patterns in reducing TT. The application of this methodology leads to significant improvements in testing efficiency. This study effectively determines the optimal multi-voltage and temperature parameters for IC testing. By leveraging automatic pattern generation and compression techniques, it achieves a substantial reduction in both test data and TT. The findings emphasize the importance of adhering to the DFT principles of observability and controllability to maximize TC. The proposed methodology demonstrates clear improvements in TDV and TT efficiency, contributing not only to the field of IC manufacturing but also emphasizing the value of a systematic and comprehensive approach to DFT in enhancing the reliability and performance of ICs.

Keywords

Design for testability (DFT), Test coverage (TC), Test time (TT), Test data volume (TDV), Automatic test pattern generation (ATPG), Observability and controllability.

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