Abstract

The Testing plays vital role to ensure the correctness of chip functionality. Boundary scan is a structured design-for-test technique which makes digital I/O pins testable by means of inserting boundary scan cells between core logic and pins. It enhances chips accessibility and testability. This project has implemented the Boundary scan on 28 nm SOC having approximated 5 million gate counts. Total pin count of SOC is 107.The project work is done on Linux platform. Tcl scripting language is used for setting parameters for design and placing runs on servers. File manipulations are done in Vi editor. BSCAN is done using Tessent BSCAN tool from Mentor Graphics. The simulations are carried out on NC Verilog simulator from Cadence. The outcome of project is, Gate level Netlist with BSCAN architecture inserted. The BSCAN cells inserted have length of 146. To cover entire SOC, the scan insertion and MBIST can be performed.

Keyword

Boundary Scan (BSCAN), SoC, Mentor Graphics, Tcl (Tool command language).

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