Implementation of MAC by using Modified Vedic Multiplier
Sreelekshmi M. S., Farsana F. J., Jithin Krishnan, Rajaram S, Aneesh R
Abstract
Multiplier Accumulator Unit (MAC) is a part of Digital Signal Processors. The speed of MAC depends on the speed of multiplier. So by using an efficient Vedic multiplier which excels in terms of speed, power and area, the performance of MAC can be increased. For this fast method of multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among various method of multiplication in Vedic mathematics, Urdhva Tiryagbhyam is used and the multiplication is for 32 X 32 bits. Urdhva Tiryagbhyam is a general multiplication formula applicable to all cases of multiplication. Adder used is Carry Look Ahead adder. The proposed design shows improvement over carry save adder.
Keyword
MAC, Vedic multiplier, VHDL, Carry Look Ahead adder.