Abstract

Hardware/software co-simulation improves the performance of embedded applications by executing the applications on a virtual platform before the actual hardware is available in silicon. However, the virtual platform of the target architecture is often not available during early stages of the embedded design flow. Consequently, analysis for parallel execution without performing hardware/software co-simulation is required. This article presents an analysis methodology for parallel execution of video encoding applications targeting heterogeneous reconfigurable architectures without performing HW/SW co-simulation. We formulate the application performance on the target architecture with an equation. The equation shows the overhead factors that reduces the speedup of parallel execution. H264 video encoding application is taken as a case study.

Keyword

Parallel execution, application analysis, heterogeneous reconfigurable architectures, video encoding.

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